1. Technical Field
The present invention relates to a test apparatus and a test method.
2. Related Art
Japanese Patent Application Publication No. 2006-278949 describes an examination apparatus for examining a plurality of semiconductor integrated circuits formed on a single wafer collectively. This can improve productivity by shortening the examination time required per wafer.
In accordance with improvement in integration and increase in size of the substrate, the size of the test target when testing each substrate has become enormous. By providing the same number of test circuits and contact terminals as the number of the semiconductor integrated circuits, the size of the test apparatus becomes large. Therefore, test apparatuses have become large and expensive, which impacts the manufacturing cost of the semiconductor apparatuses.